`timescale 1ns/1ps
module tb ();

	bit wr_clk , rd_clk ;
	bit rst_n ;
	logic rd_en , wr_en ;
	logic [16-1 : 0 ] data_in ;
	logic vaild ;
	logic empty , full ;
	logic [16 -1: 0 ] data_o ;

	always #2 wr_clk = ~wr_clk ;
	always #5 rd_clk = ~rd_clk ;


	initial begin
		wr_clk <= 0 ;
		rd_clk <= 0 ;
		rst_n <= 0 ;
		#10 ;
		rst_n <= 1 ;

		#200 ;
		$finish;
	end

	always #5 random_input_task(rd_en,wr_en,data_in);


	task random_input_task ;
		output rd_en ;
		output wr_en ;
		output [16-1 : 0 ] data;
		rd_en = $urandom_range(1, 0 ) ;
		wr_en = $urandom_range(1, 0 ) ;
		data =  $urandom_range((2**16-1), 0 ) ;

	endtask // init
	top #(
			.ADDR_WIDTH(8),
			.DATA_WIDTH(16),
			.FIFO_DEPTH(256)
		) fifo_asyn (
			.wr_clk  (wr_clk),
			.wr_en   (wr_en),
			.rd_clk  (rd_clk),
			.rd_en   (rd_en),
			.rst_n   (rst_n),
			.data_in (data_in),
			.vaild   (vaild),
			.data_o  (data_o),
			.empty   (empty),
			.full    (full)
		);

	initial begin
		$dumpfile("wave.vcd" );
		$dumpvars(0, tb ) ;
		for(int dumpmem = 0 ; dumpmem < 256 ;dumpmem++)begin
			$dumpvars(0,fifo_asyn.fifo_ram[dumpmem]);
		end
	end
endmodule : tb